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Agilent HFBR-5710L/LP Small Form Factor Pluggable Optical Transceiver for Gigabit Ethernet (1.25 GBd)
Data Sheet
Applications * Switch to switch interface * Switched backplane applications * File server interface * iSCSI applications Description The HFBR-5710L optical transceiver is compliant with the specifications set forth in both the IEEE802.3 (1000BASE-SX), and the Small Form-Factor Pluggable (SFP) Multi-Source Agreement (MSA). Its primary application is servicing Gigabit Ethernet links between optical networking equipment. It offers previously unavailable system cost, upgrade, and reliability benefits by virtue of being hot-pluggable. Further, it incorporates the latest 3.3 VDC compatible transceiver technology including an 850 nm VCSEL transmitter as well as a convenient LC-Duplex optical interface. Features * IEEE 802.3 Gigabit Ethernet (1.25 GBd) 1000BASE-SX compliant * Small Form Factor Pluggable (SFP) Multi-Source Agreement (MSA) compliant * Manufactured in an ISO 9001 compliant facility * Hot-pluggable * Optional extended de-latch for high density applications as shown in Figure 10 - HFBR-5710LP extended de-latch - HFBR-5710L standard de-latch * +3.3 V DC power supply * Industry leading EMI performance for high port density * 850 nm Vertical Cavity Surface Emitting Laser (VCSEL) * Eye safety certified: - US 21 CFR(J) - EN 60825-1 (+All) * LC-Duplex fiber connector compatible * Fiber compatibility: - 2 to 550 meters with 50/125 m fiber - 2 to 275 meters with 62.5/125 m fiber Related Products * HFBR-5701L: Dual specified 1.25 GBd Ethernet (1000BASE-SX) and 1.0625 GBd Fibre Channel (100-M5SN-I, 100-M6-SN-I) SFP * HFBR-5720L: 2.125 GBd Fibre Channel (200-M5-SN-I, 200-M6-SN-I) Multi-Mode SFP * HFBR-5730L: 1.0625 GBd Fibre Channel (100-M5-SN-I, 100-M6-SN-I) Multi-Mode SFP * HDMP-1687: Quad Channel SerDes IC 1.25 GBd Ethernet * HDMP-1646A: Single Channel SerDes IC for 1.25 GBd Ethernet and 1.0625 GBd Fibre Channel
OPTICAL INTERFACE
RECEIVER
AMPLIFICATION & QUANTIZATION
ELECTRICAL INTERFACE
RD+ (RECEIVE DATA) RD- (RECEIVE DATA) LOSS OF SIGNAL
INCOMING OPTICAL SIGNAL
PHOTODETECTOR
TRANSMITTER
LASER DRIVER & SAFETY CIRCUITRY
TX_DISABLE TD+ (TRANSMIT DATA) TD- (TRANSMIT DATA) TX_FAULT
OUTGOING OPTICAL SIGNAL
VCSEL
MOD-DEF2 EEPROM MOD-DEF1 MOD-DEF0
Figure 1. HFBR-5710L block diagram.
Overview The HFBR-5710L offers maximum flexibility to designers, manufacturers, and operators of Gigabit Ethernet networking equipment. A pluggable architecture allows the module to be installed into MSA standard SFP ports at any time - even with the host equipment operating and online. This facilitates the rapid configuration of equipment to precisely the user's needs - reducing inventory costs and network downtime. Compared with traditional transceivers, the size of the Small Form Factor package enables higher port densities. Module Diagrams Figure 1 illustrates the major functional components of the HFBR-5710L. The external configuration of the module is depicted in Figure 7. Figure 8 depicts the panel and host board footprints. Installation The HFBR-5710L can be installed in or removed from any MSAcompliant Pluggable Small Form
Factor port regardless of whether the host equipment is operating or not. The module is simply inserted, electrical-interface first, under finger-pressure. Controlled hot-plugging is ensured by 3-stage pin sequencing at the electrical interface. This printed circuit board card-edge connector is depicted in Figure 2.
As the HFBR-5710L is inserted, first contact is made by the housing ground shield, discharging any potentially component-damaging static electricity. Ground pins engage next and are followed by Tx and Rx power supplies. Finally, signal lines are connected. Pin functions and sequencing are listed in Table 2.
321
321 20 19 18 17 16 15 14 13 12 11 VEET TD- TD+ VEET VCCT VCCR VEER RD+ RD- VEER TOP OF BOARD ENGAGEMENT SEQUENCE 1 2 3 4 5 6 7 8 9 10 VEET TX FAULT TX DISABLE MOD-DEF(2) MOD-DEF(1) MOD-DEF(0) RATE SELECT LOS VEER VEER
BOTTOM OF BOARD (AS VIEWED THROUGH TOP OF BOARD)
Figure 2. Pin description of the SFP electrical interface.
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Before extracting the module, the black plastic tab beneath the optical port must be depressed, releasing the latch mechanism. The transceiver can then be pulled out of the port manually by gripping the side of the LC ports. For easier fingertip delatching in high port density applications, an optional extended tab is offered as shown in Figure 10. Serial Identification (EEPROM) The HFBR-5710L features an EEPROM for Serial ID. It contains the product data stored for retrieval by host equipment. This data is accessed via the 2wire serial EEPROM protocol of the ATMEL AT24C01A or similar in compliance with the industry standard SFP Multi-Source Agreement. Contents of the HFBR-5710L serial ID memory are displayed in Table 9. Transmitter Section The transmitter section includes the Transmitter Optical Subassembly (TOSA) and laser driver circuitry. The TOSA, containing an 850 nm VCSEL (Vertical Cavity Surface Emitting Laser) light source, is located at the optical interface and mates with the LC optical connector. The TOSA is driven by a custom IC, which converts differential logic signals into an analog laser diode drive current. This Tx driver circuit regulates the optical power at a constant level provided the data pattern is DC balanced (8B10B code for example). Tx Disable The HFBR-5710L accepts a transmit disable control signal input which shuts down the transmitter. A high signal implements this function while a low signal allows normal laser
operation. In the event of a fault (e.g., eye safety circuit activated), cycling this control signal resets the module as depicted in Figure 6. Eye Safety Circuit The HFBR-5710L provides Class 1 eye safety by design and has been tested for compliance with the requirements listed in Table 1. The eye safety circuit continuously monitors optical output power levels and will disable the transmitter and assert a TX_FAULT signal upon detecting an unsafe condition. Such unsafe conditions can be created by inputs from the host board (Vcc fluxuation, unbalanced code) or faults within the module. Receiver Section The receiver section includes the Receiver Optical Subassembly (ROSA) and amplification/ quantization circuitry. The ROSA, containing a PIN photodiode and custom trans-impedance preamplifier, is located at the optical interface and mates with the LC optical connector. The ROSA is mated to a custom IC that provides post-amplification and quantization. Also included is a Loss Of Signal (LOS) detection circuit.
Loss of Signal The Loss Of Signal (LOS) output indicates an unusable optical input power level. A high LOS output signal indicates a loss of signal while a low LOS output signal indicates normal operation. The Loss Of Signal thresholds are set to indicate a definite optical fault has occurred (e.g., disconnected or broken fiber connection to receiver, failed transmitter, etc.). Functional I/O The HFBR-5710L accepts industry standard differential signals such as LVPECL and CML within the scope of the SFP MSA. To simplify board requirements, transmitter bias resistors and coupling capacitors are incorporated into the transceiver module. The module is "accoupled" and internally terminated. Figure 4 illustrates a recommended interface circuit to link the HFBR-5710L to the supporting Physical Layer integrated circuits. Timing diagrams for the MSA compliant control signals implemented in this module are depicted in Figure 6.
1 H VCCT 0.1 F
1 H VCCR 0.1 F 10 F 0.1 F 10 F 3.3 V
SFP MODULE
HOST BOARD
Figure 3. MSA required power supply filter.
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Required Host Board Components The MSA power supply noise rejection filter is required on the host PCB to meet data sheet performance. The MSA filter incorporates an inductor which should be rated 400 mADC and 1 series resistance or better. It should not be replaced with a ferrite. The required filter is illustrated in Figure 3. The MSA also specifies that 4.7 K to 10 K pull-up resistors for TX_FAULT, LOS, and MOD_DEF0,1,2 are required on the host PCB. Application Support Evaluation Kit To assist in the transceiver evaluation process, Agilent offers a 1.25 Gbd Gigabit Ethernet evaluation board which facilitates testing of the HFBR-5710L. It can be obtained through the Agilent Field Organization by referencing Agilent part number HFBR-0571. Reference Designs A Reference Design including the HFBR-5710L and the HDMP1687 GigaBit Quad SerDes is available. It may be obtained through the Agilent Field Sales organization. Regulatory Compliance See Table 1 for transceiver Regulatory Compliance. Certification level is dependent on the overall configuration of the host equipment. The transceiver performance is offered as a figure of merit to assist the designer.
Electrostatic Discharge (ESD) There are two design cases in which immunity to ESD damage is important. The first case is during handling of the transceiver prior to insertion into the transceiver port. To protect the transceiver, it's important to use normal ESD handling precautions. These precautions include using grounded wrist straps, work benches, and floor mats in ESD controlled areas. The ESD sensitivity of the HFBR-5710L is compatible with typical industry production environments. The second case to consider is static discharges to the exterior of the host equipment chassis after installation. To the extent that the optical interface is exposed to the outside of the host equipment chassis, it may be subject to system-level ESD requirements. Immunity The ESD performance of the HFBR-5710L exceeds typical industry standards. Equipment hosting HFBR-5710L modules will be subjected to radio-frequency electromagnetic fields in some environments. The transceiver has good immunity to such fields due to its shielded design. Electromagnetic Interference (EMI) Equipment incorporating Gigabit Ethernet transceivers is typically required to meet the requirements of the FCC in the United States, CENELEC EN55022 (CISPR 22) in Europe, and VCCI in Japan.
The metal housing and shielded design of the HFBR-5710L minimize the EMI challenge facing the host equipment designer. Flammability The HFBR-5710L transceiver is made of metal and high strength, heat resistant, chemically resistant, and UL 94V-0 flame retardant plastic. Caution There are no user serviceable parts nor any maintenance required for the HFBR-5710L. All adjustments are made at the factory before shipment to our customers. Tampering with, modifying, misusing or improperly handling the HFBR-5710L will void the product warranty. It may also result in improper operation of the HFBR-5710L circuitry, and possible overstress of the laser source. Device degradation or Product failure may result. Connection of the HFBR-5710L to a non-Gigabit Ethernet-compliant optical source, operating above the recommended absolute maximum conditions or operating the HFBR-5710L in a manner inconsistent with its design and function may result in hazardous radiation exposure and may be considered an act of modifying or manufacturing a laser product. The person(s) performing such an act is required by law to recertify and re-identify the laser product under the provisions of U.S. 21 CFR (Subchapter J).
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1 H VCCT,R 10 F 0.1 F 1 H HOUSING GROUND
*RES
VCCT 0.1 F *RES
AGILENT HFBR-5710L
GP04 TX_FAULT VREFR TX[0:9] TBC EWRAP SYNC LOOP SO1+ SO1- 50 50 C C
TX_DISABLE TX_FAULT TD+ R TD- VEET VCCR LASER DRIVER & EYE SAFETY CIRCUITRY
MAC ASIC
RBC RX_RATE
AGILENT HDMP-1687
RX[0:9] SYN1 RC1(0:1) RCM0 RFCT SI1+ R SI1- VCCT,R *RES *RES *RES 50 50
10 F
0.1 F
RD+ C C RD- AMPLIFICATION & QUANTIZATION
RX_LOS
REF_RATE *RES RX_LOS MOD_DEF2 MOD_DEF1 MOD_DEF0 VEER NOTE: * 4.7 k < RES < 10 k EEPROM
GPIO(X) GPIO(X) GP14 REFCLK 125 MHz
Figure 4. Typical application configuration.
Table 1. Regulatory Compliance Feature Electrostatic Discharge (ESD) to the Electrical Pins Electrostatic Discharge (ESD) to the Duplex LC Receptacle Test Method JEDEC/EIA JESD22-A114-A Variation of IEC 6100-4-2 Performance Class 2 (> +2000 Volts) Typically withstands at least 25 kV without damage when the duplex LC connector receptacle is contacted by a Human Body Model probe Applications with high SFP port counts are expected to be compliant; however, margins are dependent on customer board and chassis design. Typically shows a negligible effect from a 10 V/m field swept from 80 to 1000 MHz applied to the transceiver without a chassis enclosure. CDRH certification #9720151-13 TUV file #E9971083.07 UL File #E173874
Electromagnetic Interference (EMI) Immunity
FCC Class B CENELEC EN55022 Class B (CISPR 22A) VCCI Class 1 Variation of IEC 61000-4-3
Eye Safety[1]
US FDA CDRH AEL Class 1 EN(IEC)60825-1,2, EN60950 Class 1 Underwriters Laboratories and Canadian Standards Association Joint Component Recognition for Information Technology Equipment Including Electrical Business Equipment
Component Recognition
Note: 1. Changes to IEC 60825-1,2 are currently anticipated to allow higher eye-safe Optical Output Power levels. Agilent may choose to take advantage of these in future revisions to this part.
5
Table 2. Pin Description Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VeeT TX Fault TX Disable MOD-DEF2 MOD-DEF1 MOD-DEF0 LOS VeeR VeeR VeeR RDRD+ VeeR VccR VccT VeeT TD+ TDVeeT Function/Description Transmitter Ground Transmitter Fault Indication Transmitter Disable - Module disables on high or open Module Definition 2 - Two wire serial ID interface Module Definition 1 - Two wire serial ID interface Module Definition 0 - Grounded in module Loss of Signal Receiver Ground Receiver Ground Receiver Ground Inverse Received Data Out Received Data Out Receiver Ground Receiver Power - 3.3 V 5% Transmitter Power - 3.3 V 5% Transmitter Ground Transmitter Data In Inverse Transmitter Data In Transmitter Ground Engagement Order (insertion) 1 3 3 3 3 3 3 3 1 1 1 3 3 1 2 2 1 3 3 1 7 7 6 6 5 5 4 1 2 3 3 3 Notes
Rate Select Not Connected
Notes: 1. TX Fault is an open collector/drain output which should be pulled up externally with a 4.7K - 10 K resistor on the host board to a supply < VccT+0.3 V or VccR+0.3 V. When high, this output indicates a laser fault of some kind. Low indicates normal operation. In the low state, the output will be pulled to < 0.8 V. 2. TX disable input is used to shut down the laser output per the state table below. It is pulled up within the module with a 4.7-10 K resistor. Low (0 - 0.8 V): Transmitter on Between (0.8 V and 2.0 V): Undefined High (2.0 - 3.465 V): Transmitter Disabled Open: Transmitter Disabled 3. Mod-Def 0,1,2. These are the module definition pins. They should be pulled up with a 4.7-10 K resistor on the host board to a supply less than VccT +0.3 V or VccR+0.3 V. Mod-Def 0 is grounded by the module to indicate that the module is present Mod-Def 1 is clock line of two wire serial interface for optional serial ID Mod-Def 2 is data line of two wire serial interface for optional serial ID 4. LOS (Loss of Signal) is an open collector/drain output which should be pulled up externally with a 4.7 K - 10 K resistor on the host board to a supply < VccT,R+0.3 V. When high, this output indicates the received optical power is below the worst case receiver sensitivity (as defined by the standard in use). Low indicates normal operatio0n. In the low state, the output will be pulled to < 0.8 V. 5. RD-/+: These are the differential receiver outputs. They are AC coupled 100 differential lines which should be terminated with 100 differential at the user SERDES. The AC coupling is done inside the module and is thus not required on the host board. The voltage swing on these lines must be between 370 and 2000 mV differential (185 - 1000 mV single ended) according to the MSA. Typically it will be 1500mv differential. 6. VccR and VccT are the receiver and transmitter power supplies. They are defined as 3.135 - 3.465 V at the SFP connector pin. The in-rush current will typically be no more than 30 mA above steady state supply current after 500 nanoseconds. 7. TD-/+: These are the differential transmitter inputs. They are AC coupled differential lines with 100 differential termination inside the module. The AC coupling is done inside the module and is thus not required on the host board. The inputs will accept differential swings of 500 - 2400 mV (250 - 1200 mV single ended). However, the applicable recommended differential voltage swing is found in Table 5.
6
Table 3. Absolute Maximum Ratings Parameter Ambient Storage Temperature (Non-Operating) Case Temperature Relative Humidity Supply Voltage Voltage at any Input Pin Sense Output Current - LOS, TX Fault Sense Output Current - MOD_DEF2 Symbol Ts TC RH VCCT,R VIH ID ID Minimum -40 -40 5 -0.5 -0.5 Maximum +100 +85 95 3.6 VCC 150 5 Unit C C % V V mA mA Notes 1 1 1 1 1 1 1
Notes: 1. Absolute Maximum Ratings are those values beyond which damage to the device may occur if these limits are exceeded. See Reliability Data Sheet for specific reliability performance. 2. Between Absolute Maximum Ratings and the Recommended Operating Conditions functional performance is not intended, device reliability is not implied, and damage to the device may occur.
Table 4. Recommended Operating Conditions Parameter Case Temperature Supply Voltage Date Rate Symbol TC VCC Minimum 0 3.135 Typical 25 3.3 1.25 Maximum 70 3.465 Unit C V Gb/s Notes 1, 2 1 1
Notes: 1. Recommended Operating Conditions are those within which functional performance within data sheet characteristics is intended. 2. Refer to the Reliability Data Sheet for specific reliability performance predictions.
Table 5. Transceiver Electrical Characteristics (TC = 0C to 70C, VCCT,R = 3.3 V 5%) Parameter Module Supply Current Power Dissipation Power Supply Noise Rejection (peak-peak) Data Input: Transmitter Differential Input Voltage (TD +/-) Data Output: Receiver Differential Output Voltage (RD +/-) Receive Data Rise & Fall Times Sense Outputs: Transmit Fault [TX_FAULT, Loss of Signal (LOS), MOD_DEF2] Control Inputs: Transmitter Disable [TX_DISABLE, MOD_DEF1,2] Symbol ICC PDISS PSNR Minimum Typical 160 530 100 Maximum 220 765 Unit mA mW mVPP 1 Notes
VI
500
1660
mVPP
2
VO Trf
370
1500 220
2000
mVPP ps
3
VOH
2.0
VCC
V
VOL VIH VIL
0 2.0 0
0.8 VCC 0.8
V V V
Notes: 1. Measured at the input of the required MSA Filter on host board. 2. Internally AC coupled and terminated to 100 differential load. 3. Internally AC coupled, but requires a 100 ohm differential termination at or internal to Serializer/Deserializer.
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Table 6. Transmitter Optical Characteristics (TC = 0C to 70C, VCCT,R = 3.3 V 5%) Parameter Output Optical Power (Average) Optical Extinction Ratio Center Wavelength Spectral Width - rms Optical Rise/Fall Time Relative Intensity Noise, maximum Total Jitter (TP1 to TP2 Contribution) Pout TX_DISABLE Asserted POFF Symbol Pout ER C Trise/fall RIN TJ 150 Minimum -9.5 9 830 Typical -6.5 14.5 850 860 0.85 260 -117 227 0.284 -35 Maximum 0 Unit dBm dB nm nm ps dB/Hz ps UI dBm Notes 1, 2, 3 1 1 1 1 1 1 1 1
Notes: 1. IEEE 802.3. 2. Max. Pout is the lesser of 0 dBm or Maximum allowable per Eye Safety Standard. 3. 50/125 m fiber with NA = 0.2, 62.5/125 m fiber with NA = 0.275.
NORMALIZED TIME (UNIT INTERVAL) 0 130 0.22 0.375 0.625 0.78 1.0 1.30 1.00 0.80 0.50 0.20 0 -0.20 0 22 37.5 62.5 78 100
NORMALIZED AMPLITUDE (%)
100 80 50 20 0 -20
NORMALIZED TIME (% OF UNIT INTERVAL)
NORMALIZED AMPLITUDE
Figure 5a. Gigabit Ethernet transmitter eye mask diagram.
Figure 5b. Typical HFBR-5710L eye mask diagram.
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Table 7. Receiver Optical Characteristics (TC = 0C to 70C, VCCT,R = 3.3 V 5%) Parameter Optical Input Power Receiver Sensitivity (Optical Input Power) Stressed Receiver Sensitivity Total Jitter (TP3 to TP4 Contribution) Return Loss LOS De-Asserted LOS Asserted LOS Hysterisis
Notes: 1. IEEE 802.3. 2. 62.5/125 m fiber. 3. 50/125 m fiber.
Symbol PR PRMIN
Minimum -17
Typical -21
Maximum 0 -17 -12.5 -13.5
Unit dBm dBm dBm dBm ps UI dB dBm dBm dB
Notes 1 1 1, 2 1, 3 1 1 1 1 1 1
TJ
266 0.332 -12
PD PA PD - PA -31 3
-17
Table 8. Transceiver Timing Characteristics (TC = 0C to 70C, VCCT,R = 3.3 V 5%) Parameter Tx Disable Assert Time Tx Disable Negate Time Time to initialize, including reset of Tx_Fault Tx Fault Assert Time Tx Disable to Reset LOS Assert Time LOS Deassert Time Serial ID Clock Rate Symbol t_off t_on t_init t_fault t_reset t_loss_on t_loss_off f_serial_clock 10 100 100 100 Minimum Typical Maximum 10 1 300 100 Unit s ms ms s s s s kHz Notes 1 2 3 4 5 6 7
Notes: 1. Time from rising edge of Tx Disable to when the optical output falls below 10% of nominal. 2. Time from falling edge of Tx Disable to when the modulated optical output rises above 90% of nominal. 3. From power on or negation of Tx Fault using Tx Disable. 4. Time from fault to Tx fault on. 5. Time Tx Disable must be held high to reset Tx_fault. 6. Time from LOS state to Rx LOS assert. 7. Time from non-LOS state to RX LOS deassert.
9
VCC > 3.15 V TX_FAULT TX_DISABLE TRANSMITTED SIGNAL t_init
VCC > 3.15 V TX_FAULT TX_DISABLE TRANSMITTED SIGNAL t_init
t-init: TX DISABLE NEGATED
t-init: TX DISABLE ASSERTED
VCC > 3.15 V TX_FAULT TX_DISABLE TRANSMITTED SIGNAL t_init INSERTION
TX_FAULT TX_DISABLE TRANSMITTED SIGNAL t_off t_on
t-init: TX DISABLE NEGATED, MODULE HOT PLUGGED
t-off & t-on: TX DISABLE ASSERTED THEN NEGATED
OCCURANCE OF FAULT TX_FAULT TX_DISABLE TRANSMITTED SIGNAL t_fault
OCCURANCE OF FAULT TX_FAULT TX_DISABLE TRANSMITTED SIGNAL
* SFP SHALL CLEAR TX_FAULT IN t_init IF THE FAILURE IS TRANSIENT
t_reset
t_init*
t-fault: TX FAULT ASSERTED, TX SIGNAL NOT RECOVERED
t-reset: TX DISABLE ASSERTED THEN NEGATED, TX SIGNAL RECOVERED
OCCURANCE OF FAULT OPTICAL SIGNAL TX_FAULT TX_DISABLE TRANSMITTED SIGNAL t_fault2 t_reset
* SFP SHALL CLEAR Tx_FAULT IN t_init IF THE FAILURE IS TRANSIENT
OCCURANCE OF LOSS LOS t_loss_on t_loss_off
t_init*
t-fault2: TX DISABLE ASSERTED THEN NEGATED, TX SIGNAL NOT RECOVERED NOTE: t_fault2 timing is typically 1.7 to 2 ms.
t-loss-on & t-loss-off
Figure 6. Transceiver timing diagrams (Module installed except where noted).
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Table 9. EEPROM Serial ID Memory Contents Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Hex 03 04 07 00 00 00 01 20 40 0C 00 01 0C 00 00 00 37 1B 00 00 41 47 49 4C 45 4E 54 20 20 20 20 20 A G I L E N T ASCII Address 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Hex 20 20 20 20 00 00 30
D3
ASCII
Address 64 65 66 67 68 69 70 71
Hex 00 1A 00 00 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 00 00 00 Note 3
ASCII
Address 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
Hex Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4
ASCII
48 46 42 52 2D 35 37 31 30 4C 20 20 20 20 20 20 20 20 20 20 00 00 00 A9
H F B R 5 7 1 0 L
72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95
Notes: 1. These addresses are reserved for serial number information and will vary from module to module. 2. These addresses are reserved for date code information and may vary from lot to lot. 3. Byte address 95 is a check sum which may vary from module to module. 4. These fields are reserved for future use by Agilent Technologies.
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AGILENT HFBR-5710L 850 nm LASER PROD 21CFR(J) CLASS 1 COUNTRY OF ORIGIN YYWW TUV XXXXXX UL
TX
RX
13.40 0.1 (0.53 0.004)
13.75 0.1 (0.54 0.004)
56.40 0.2 (2.22 0.01)
SEE DETAIL 1
TCASE REFERENCE POINT
AREA FOR PROCESS PLUG
13.0 0.1 (0.51 0.004)
14.8 MAX. UNCOMPRESSED (0.58)
14.20 0.1 (0.56 0.004) DETAIL 1 SCALE 2x
0.7 MAX. UNCOMPRESSED (0.03)
FRONT EDGE OF SFP TRANSCEIVER CAGE
6.25 0.05 (0.25 0.002)
8.50 0.1 (0.33 0.004)
11.80 0.2 (0.46 0.008)
DIMENSIONS ARE IN MILLIMETERS (INCHES)
TX
RX
Figure 7. Module drawing.
12
Y
X 34.5 3x 10 10x 1.05 0.01 0.1 S X A S B 1 7.2 2.5 2.5 7.1 0.85 0.05 0.1 S X Y A 1 3.68
16.25 MIN. PITCH PCB EDGE
5.68 8.58 11.08 16.25 14.25 REF.
PIN 1
20
2x 1.7
8.48 9.6 11.93
10
11
4.8
SEE DETAIL 1 11x 2.0 11x 2.0 26.8 3 41.3 42.3 3x 10 5 9x 0.95 0.05 0.1 L X A S 2
5 3.2 0.9
20x 0.5 0.03 0.06 S A S B S
NOTES:
PIN 1 20
1.PADS AND VIAS ARE CHASSIS GROUND. 10.53 11.93 2.THROUGH HOLES, PLATING OPTIONAL. 3.HATCHED AREA DENOTES COMPONENT AND TRACE KEEPOUT (EXCEPT CHASSIS GROUND). 4.AREA DENOTES COMPONENT KEEPOUT (TRACES ALLOWED).
10.93 9.6 0.8 TYP.
11 10
4 2x 1.55 0.05 0.1 L A S B S DETAIL 1 2 0.05 TYP. 0.06 L A S B S DIMENSIONS IN MILLIMETERS
Figure 8. SFP host board mechanical layout.
13
1.7 0.9 (0.07 0.04) 3.5 0.3 (0.14 0.01) 41.73 0.5 (1.64 0.02)
PCB
BEZEL
15 MAX. (0.59)
AREA FOR PROCESS PLUG
CAGE ASSEMBLY 15.25 0.1 (0.60 0.004) 11 REF. (0.43) 9.8 MAX. (0.39) 1.5 REF. (0.06) BELOW PCB 10 REF (0.39) TO PCB 0.4 0.1 (0.02 0.004) BELOW PCB 10.4 0.1 (0.41 0.004)
16.25 0.1 MIN. PITCH (0.64 0.004)
MSA-SPECIFIED BEZEL
DIMENSIONS ARE IN MILLIMETERS (INCHES).
Figure 9. Assembly drawing.
Figure 10. The extended de-latch for belly to belly application.
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www.semiconductor.agilent.com Data subject to change. Copyright (c) 2001 Agilent Technologies, Inc. June 26, 2001 Obsoletes 5988-2462EN 5988-3323EN

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